decode4_7.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 25 行

module decode4_7(decodeout,indec);

output[7:0] decodeout;
input[3:0] indec;
reg[7:0] decodeout;

always @(indec)

   begin
      case(indec)
      
      4'd0:decodeout=8'b11000000;
      4'd1:decodeout=8'b11111001;
      4'd2:decodeout=8'b10100100;
      4'd3:decodeout=8'b10110000;
      4'd4:decodeout=8'b10011001;
      4'd5:decodeout=8'b10010010;
      4'd6:decodeout=8'b10000010;      
      4'd7:decodeout=8'b11111000;
      4'd8:decodeout=8'b10000000;
      4'd9:decodeout=8'b10010000;
      default:decodeout=8'bx;
      endcase
    end
endmodule