devfreq32.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 24 行

module devfreq32(in,reset,out);

input in,reset;
output out;
reg out;
reg[3:0] count;

always @(posedge in or negedge reset)
  begin
     if(~reset)     
            begin
            count=0;
            out=0;
            end
     else
            if(count==4'hf)
               begin 
               count=0;
               out=~out;
               end
            else  
               count=count+1;
  end
endmodule