count60.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 41 行

module count60 (clk,reset,out,cout);

input clk;
input reset;
output[7:0] out;
output  cout;

reg[7:0] out;
reg cout;

always @ (posedge clk or negedge reset)
   begin
   if(reset==0)    
      begin
	    out=0;
	    cout=0;
	    end
   else
      begin
      if(out[3:0]==9)   
        begin
        out[3:0]=0;
        if(out[7:4]==5) 
	     begin
		out[7:4]=0;
		cout=1;
		end
        else
        out[7:4]=out[7:4]+1;
        end
      else        
	 begin
	 out[3:0]=out[3:0]+1;
	 cout=0;
	 end
      end     
   end

//assign cout=((out==8'h59)&clk)?1:0;

endmodule