display.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 19 行

module display (datalow,datahigh,freq1k,reset,displaydata,sl1,sl2,sl3,sl4);

input[7:0] datalow,datahigh;
input reset,freq1k;
output[7:0] displaydata;
output sl1,sl2,sl3,sl4;

wire[7:0] lowg,lows,highg,highs;
 

decode4_7 lowone(.decodeout(lowg),.indec(datalow[3:0]));
decode4_7 lowtwo(.decodeout(lows),.indec(datalow[7:4]));
decode4_7 highone(.decodeout(highg),.indec(datahigh[3:0]));
decode4_7 hightwo(.decodeout(highs),.indec(datahigh[7:4]));

leddisplay display(.inmin({highs,highg}),.insec({lows,lowg}),.freq1k(freq1k),.reset(reset),.dataout(displaydata),.sl1(sl1),.sl2(sl2),.sl3(sl3),.sl4(sl4));

endmodule