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V 的代码
udeviceintf.v
module Udeviceintf
(
// inputs from sie
usbclock, // 12 MHz clock
usbreset, // usb reset signal
turnaround,
userialeng.v
module Userialeng
(
// inputs from bus
testmode,
testreset,
clock48, // 48 MHz clock
rcvin, // differential in
vpin, // plus in
vmin, // minus in
ufiforx.v
module Ufiforx (
setcmdwr,
getdata,
mcclock,
usbclock,
mmcreset,
syncreset,
fifowr,
fiford,
fifowrdata,
fiforddata,
fifordready,
fifowrready,
datapa
uparts.v
/****************************************************************************
*
* parts.v - company wide parts mapping file. this is RTL for the parts
* we instantiate. use this f
usiecrc.v
module Usiecrc
(
// inputs
usbclock,
usbreset,
rcvdatavalid,
rcvdatabit,
rcvcrc5data,
rcvcrc5check,
rcvcrc16data,
rcvcrc16check,
xmitdatavalid,
xmitdatabit,
xmitcr
usbmonitor.v
// THIS BLOCK INCLUDES 8051IF
module Usbmonitor
(
// inputs from bus
pwronreset,
clock48, // 48 MHz clock
rcvin, // differential in
vpin, // plus in
vmin, // minus in
vm
ubulkfifotx.v
//`timescale 1ns / 100ps
module Ubulkfifotx (
syncreset,
BCLK,
usbclock,
dff2wr,
dff2rd,
dff2wrdata,
dff2rddata,
dff2rdready,
dff2wrready,
datapacketok,
//
udevsof.v
/******************************************
Filename: devsof.v 1.6
******************************************/
/*
The device start of frame counter/generator keeps track
of Start Of Frame (SOF
usbtop.v
// THIS BLOCK INCLUDES 8051IF
module Usbtop
(
// inputs from bus
pwronreset,
clock48, // 48 MHz clock
rcvin, // differential in
vpin, // plus in
vmin, // minus in
vmo,
udevrom.v
/*
The device rom contains the bytes for the get confuration
cycles.
This is the version for the usb camera core application.
*/
module Udevrom
(
// inputs from dev
devromdescriptorin