udevsof.v

实现USB接口功能的VHDL和verilog完整源代码

/******************************************
	Filename: 	devsof.v 1.6
******************************************/
/* 
The device start of frame counter/generator keeps track
of Start Of Frame (SOF) and synthesizes an SOF if one doesn't
come.  This guarantees an ISO endpoint stays in sync even if the
SOF token gets garbled.
*/

module Udevsof
	(
	// inputs from sie
		usbclock,	// 12 MHz clock
		usbreset,	// usb reset signal
		rcvsof,
		hstframenumber,
		framenumber,

	// outputs to device
		synthsof
	);

input	usbclock;	// 12 MHz clock
input	usbreset;	// synopsys sync_set_reset "usbreset"
input	rcvsof;
input	[10:0]	hstframenumber;
output	[10:0]	framenumber;
output	synthsof;

`include "Usiecntrdef.v"

reg	[13:0]	cyclecount;
reg	[10:0]	framenumber;
reg	synthsof;
reg	holdoffsof;

wire	maxsof = (cyclecount == MAXSOF);

always @(posedge usbclock)
begin
	if (usbreset || rcvsof || maxsof)
		cyclecount <= 14'h0000;
	else
		cyclecount <= cyclecount + 1'b1;

	if (rcvsof)
		framenumber <= hstframenumber;
	else if (maxsof)
		framenumber <= framenumber + 1;	// increment on maxsof

	// send synthesized sof if the cycle count hits max, but then
	// don't pass on a real one if it comes shortly after the synthesized
	// one (don't want a double sof)
	if (usbreset)
		synthsof <= 1'b0;
	else if ((rcvsof && ~holdoffsof) || maxsof)		
		synthsof <= 1'b1;
	else
		synthsof <= 1'b0;

	if (usbreset)
		holdoffsof <= 1'b0;
	else if (maxsof)		// made one ourselves
		holdoffsof <= 1'b1;
	else if (cyclecount[6])	// reset the holdoff after, say, 64 clocks
		holdoffsof <= 1'b0;
end

endmodule