uvendorcmdinouts.v

来自「实现USB接口功能的VHDL和verilog完整源代码」· Verilog 代码 · 共 20 行

output[2:0] clockrate;
output[2:0] setmode;
output getstatus;
output getstatuscheck;
output getdata;
output setcmdwr;
output setcmdrd;
output getbusy;
output wpb;
input  gpiopin0;
input  gpiopin1;
input  gpiopin2;

output gpiopin3;
output gpiopin4;
output gpiopin5;
output gpiopin6;
output gpiopin7;