uparts.v

实现USB接口功能的VHDL和verilog完整源代码

/****************************************************************************
 * 
 * parts.v   - company wide parts mapping file. this is RTL for the parts
 *             we instantiate. use this file for your verilog simulations only.
 *             During synthesis, you'll point to the library specific mapped
 *             counterpart of this file - parts.vg  Actually you'll point to
 *             a directory where a .db exists for each part, 
 *             those .db(s) come from the parts.vg mapping.
 *             Put this in your files.v to scan this file during simulation:
 *             -v /projects/lib/files.v
 * 
 * Note : pad cells are mapped in padparts.v
 * 
 *   Cell naming convention:
 *   the first number if it has a leading "" will be how wide it is, 
 *   other numbers not
 *   surrounded by "" denote function (or2,mux2x2), if the name ends in
 *   x# the # is the drive strength. 
 * 
 *   mux2x1 - 2:1 mux
 *   mux322x1 32 bit wide 2:1 mux
 *   or2 - 2 bit or gate
 *   or2x4 - 2 bit or with 4x drive
 *   or28x2 - 8 bit wide 2 bit or with 2x drive
 *   invx4 - inverter with 4x drive
 *   bufxa - buffer with a drive
 * 
 *****************************************************************************/

module dffr (q,d,clk,rstn);
  input	 d,clk,rstn;
  output q;
  reg	 q;

always @(posedge clk or negedge rstn)
  begin
    if (rstn == 1'b0)
      q <= 1'b0;
    else
      q <= d;
  end // always @ (posedge clk or negedge rstn)
  
endmodule // dffr

module dffr_host (q,d,clk,rstn);
  input	 d,clk,rstn;
  output q;
  reg	 q;

always @(posedge clk or negedge rstn)
  begin
    if (rstn == 1'b0)
      q <= 1'b0;
    else
      q <= d;
  end // always @ (posedge clk or negedge rstn)
 endmodule 

module dff (q,qn,d,clk);
  input	 d,clk;
  output q, qn;
  reg	 q;

wire	qn = ~q;

always @(posedge clk)
  begin
      q <= d;
  end // always @ (posedge clk)
  
endmodule // dff


module latr (q,d,en,rstn);
  input  d,en,rstn;
  output q;
  reg    q;

always @(en or d or rstn or q)
  begin
    if (rstn == 1'b0)
      q <= 1'b0;
    else
      if (en == 1'b1)
        q <= d;
      else
        q <= q;
  end // always @ (en or d or negedge rstn)

endmodule // latr


module lat (q,d,en);
  input  d,en;
  output q;
  reg    q;

always @(en or d or q)
  begin
      if (en == 1'b1)
        q <= d;
      else
        q <= q;
  end // always @ (en or d)

endmodule // lat

module or2x4 (z,a,b);
input  a,b;
output z;

wire	z = a | b;

endmodule // or2x4

module invx4 (z,a);
  input	 a;
  output z;

  wire	 z = !a;
endmodule // invx4

module bufxa (z,a);
  input	 a;
  output z;

  wire	 z = a;
endmodule // bufxa

module bushold1 (i);
  input	 	i;
endmodule // bushold1

module bushold8 (i);
  input	 [7:0]	i;
endmodule // bushold8

module bushold32 (i);
  input	 [31:0]	i;
endmodule // bushold32

module mux2x1x4 (z,i0,i1,s);
input  i0,i1,s;
output z;

wire	z = (s) ? i1 : i0;

endmodule // mux2x1x4


module usbpll (clk24, clk48, xtalout, xtalin, disablepll);
input  xtalin, disablepll;
output xtalout, clk24, clk48;

reg	clk24, clk48;
wire	xtalout = 1'b1;

always @(posedge xtalin )
begin
	if (disablepll)
		clk24 <= 1'b1;
	else if (clk24 == 1) 
		clk24 <= 1'b0;
	else
		clk24 <= 1'b1;	// resolves the initial x problem
end
always @(xtalin )
begin
	if (disablepll)
		clk48 <= 1'b1;
	else
		clk48 <= xtalin;
end	// always @(xtalin)

endmodule




module ambabidirx32 (
// Outputs
	ExtOutData,
    IntInData,
	//Inputs
	ExtInData,
	IntOutData,
	Enable,
	Sel
   );
								   
  // Local copy of timing parameter
 parameter TriEn1 = 4;
													 
output [31:0] ExtOutData;       // Tri-stated output to bus
output [31:0] IntInData;        // Gated input data to slave
												   
input  [31:0] ExtInData;        // Input from bus
 input  [31:0] IntOutData;       // Output data from slave
input    Enable;           // Enable Output data
 input    Sel;              // Select the input data
															   
 assign #TriEn1 ExtOutData = Enable ? IntOutData : 'bz;
assign IntInData = Sel ? ExtInData : 'b0;
 endmodule // ambabidirx32
			 
	module ClockMux (
		OutClock,
		InClock0,
		InClock1,
		Select
			);

	  output       OutClock;           // Gated Clock out
	  input    InClock0;           // Clock in 1
	  input    InClock1;           // Clock in 2
	  input    Select;             // Clock Select

	 // If Select=0 then use Inclock0
	 assign OutClock = Select ? InClock1 : InClock0;

 endmodule // ClockMux