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lwbbuschange.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- BUS CHANGE FOR TWO SRAMS
lwbsram.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- SRAM INTERFACE
lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sdram.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
timescale.v
`timescale 1ns / 10ps
cpu.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
timescale.v
`timescale 1ns / 1ns