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utop.v
/*
# --------------------------------------------------------------------------
#
# Module : Utop.v
#
# Reviewer(s) :
#
# Revision : $Revision: 1.6 $
#
ucore.v
module Ucore
(
// inputs from bus
testmode,
testreset,
clock48, // 48 MHz clock
rcvin, // differential in
vpin, // plus in
vmin, // minus in
//
ufifo.v
module Ufifo (
mcclock,
usbclock,
syncreset,
mmcreset,
fifowr,
fiford,
fifowrdata,
fiforddata,
fifordready,
fifowrready,
datapacketok,
datapacketnotok
dffr.v
/****************************************************************************
*
* parts.v - company wide parts mapping file. this is RTL for the parts
* we instantiate. use this
usiepkt.v
/******************************************
Filename: siepkt.v 1.22
******************************************/
/*
This module creates and encodes outgoing data packets.
It takes requests fro
usiedpll.v
/******************************************
Filename: siedpll.v 1.27
******************************************/
/*
The Digital PLL module takes the incoming signal, synchronizes it through
a
uctlreg.v
// This module have a register bank for storing Commands and Cards Status
module UCtlreg (
// USB
getbusy,
getstatus,
usbclock,
syncreset,
mcclock,
mcreset,
ubulkfiforx.v
// THIS FIFO IS FO RX BUFFER
// fifo using sync_reset async fifo
module Ubulkfiforx (
BCLK,
syncreset,
usbclock,
dffwr,
dffrd,
dffwrdata,
dffrddata,
dffrdready,
usiedcd.v
/******************************************
Filename: siedcd.v 1.24
******************************************/
/*
The decoder module gets incoming data bits and decodes the packet
informatio
usbmmc.v
/*
# --------------------------------------------------------------------------
# Module : usbmmc
#
# Revision : $Revision: 1.60 $
#
#-----------------------------------