ufifo.v

实现USB接口功能的VHDL和verilog完整源代码

module Ufifo (
		 mcclock,
		 usbclock,
		 syncreset,
		 mmcreset,
		 fifowr,
		 fiford,
		 fifowrdata,
		 fiforddata,
		 fifordready,
		 fifowrready,
		 datapacketok,
		 datapacketnotok
		 );
  input          mcclock;
  input          mmcreset;
  input			 usbclock;
  input			 syncreset; 
  input			 fifowr;
  input			 fiford;
  
  parameter		 DFFDEPTH = 32,
    			 DFFWIDTH = 8,
	    		 FULL = 32,
	    		 DFFADDRWIDTH = 5;	// 2^6 is 64
  
  input [DFFWIDTH-1:0]	 fifowrdata;
  output [DFFWIDTH-1:0]  fiforddata;
 
  output		 fifordready;
  output		 fifowrready;
  input			 datapacketok;
  input			 datapacketnotok;


  reg [DFFWIDTH-1:0]	 ffdata [DFFDEPTH-1:0];
  reg [DFFADDRWIDTH:0] wraddr,rdaddr,oldwraddr;
  wire			 full,empty;
  reg           fifordready;
  reg           fifowrready; 

  always @(posedge usbclock)
    begin
      if (syncreset)
	begin
	  wraddr <= 'h0;
	  oldwraddr <= 'h0;
	end // if (syncreset)
      else
	begin
	  ffdata[wraddr[DFFADDRWIDTH-1:0]] <= (fifowr) ? fifowrdata : 
	    ffdata[wraddr[DFFADDRWIDTH-1:0]];
	  wraddr <= (fifowr) ? wraddr + 1'b1 : (datapacketnotok) ?
	    oldwraddr : wraddr;
	  oldwraddr <= (datapacketok) ? wraddr : oldwraddr;
	end // else: !if(syncreset)
    end // always @ (posedge usbclock)
 
 always@(posedge mcclock)
	 begin
	   if(mmcreset)
    	   rdaddr <='h0;
       else
	       rdaddr <= (fiford) ? rdaddr +1'b1 :rdaddr;
	 end

  wire [DFFWIDTH-1:0] fiforddata = ffdata[rdaddr[DFFADDRWIDTH-1:0]];
  assign empty = oldwraddr[DFFADDRWIDTH:0] == rdaddr[DFFADDRWIDTH:0];
  assign full = (wraddr[DFFADDRWIDTH-1:0] == rdaddr[DFFADDRWIDTH-1:0]) &&
                (wraddr[DFFADDRWIDTH] != rdaddr[DFFADDRWIDTH]);
  
  //wire fifordready =  full;
  //wire fifowrready = ~full;
  always @( posedge mcclock)  begin
    fifordready =  empty ? 0 : (full? 1: fifordready) ;
  end 

 always @(posedge usbclock)
	fifowrready = empty ? 1 : (full ?0 : fifowrready);
  
  // synopsys translate_off
  always @(posedge usbclock)
    begin
      if (full && fifowr && !fiford)
	$write ("Error :****** %m fifo overrun at time %t\n",$time);
      if (empty && ~fifowr && fiford)
	$write ("Error :****** %m fifo underrun at time %t\n",$time);
    end // always @ (posedge usbclock)

  wire [DFFWIDTH-1:0] debugdata0 = ffdata[0];
  wire [DFFWIDTH-1:0] debugdata1 = ffdata[1];
  wire [DFFWIDTH-1:0] debugdata2 = ffdata[2];
  wire [DFFWIDTH-1:0] debugdata3 = ffdata[3];
  
  wire [DFFWIDTH-1:0] debugdata4 = ffdata[4];
  wire [DFFWIDTH-1:0] debugdata5 = ffdata[5];
  wire [DFFWIDTH-1:0] debugdata6 = ffdata[6];
  wire [DFFWIDTH-1:0] debugdata7 = ffdata[7];
  // synopsys translate_on

endmodule // devfifo