ubulkfiforx.v

实现USB接口功能的VHDL和verilog完整源代码

// THIS FIFO IS  FO RX BUFFER 
// fifo using sync_reset async fifo

module Ubulkfiforx (
		 BCLK,
		 syncreset,
		 usbclock,
		 dffwr,
		 dffrd,
		 dffwrdata,
		 dffrddata,
		 dffrdready,
		 dffwrready,
//		 dmareqrx,
		 datapacketok,
		 datapacketnotok
		 );
  input          syncreset;
  input          BCLK;
  input			 usbclock;
  input			 dffwr;
  input			 dffrd;

  parameter		 DFFDEPTH = 32,
			     DFFWIDTH = 8,
			     DMAWIDTH=32,
				// ENADMA =24, //8
				// ENADMA1 =28, //12
				// DISDMA =0,
			     DFFADDRWIDTH = 5;	// 2^6 is 64

  input [DFFWIDTH-1:0]	 dffwrdata;
  output [DMAWIDTH-1:0] dffrddata;
  output		 dffrdready;
  output		 dffwrready;
  input			 datapacketok;
 // output         dmareqrx;
  input			 datapacketnotok;

  reg [DFFWIDTH-1:0]	 ffdata [DFFDEPTH-1:0];
  reg [DFFADDRWIDTH:0] wraddr,rdaddr,oldwraddr;
  wire	 full,empty;
  reg   dmareqrx;

  always @(posedge usbclock or posedge syncreset)
    begin
	  if(syncreset)  //BRES
	  begin
	  wraddr <= 'h0;
	  oldwraddr <= 'h0;
	  end // if (aBRES)
    else
	  begin
	      ffdata[wraddr[DFFADDRWIDTH-1:0]] <= (dffwr) ? dffwrdata 
	      : ffdata[wraddr[DFFADDRWIDTH-1:0]];
	      wraddr <= (dffwr) ? wraddr + 1'b1 : (datapacketnotok) ?
	      oldwraddr : wraddr;
	      oldwraddr <= (datapacketok) ? wraddr : oldwraddr;
	end // else: !if(BRES)
    end // always @ (posedge usbclock)


 always @(negedge BCLK or posedge syncreset)
   begin
	   if(syncreset)
		  rdaddr <='h0;
       else if(dffrd)
         rdaddr <= rdaddr + 4;
   end

  wire[31:0]  dffrddata = { ffdata[rdaddr[DFFADDRWIDTH-1:0] + 3], ffdata[rdaddr[DFFADDRWIDTH-1:0] +2],
						ffdata[rdaddr[DFFADDRWIDTH-1:0] +1], ffdata[rdaddr[DFFADDRWIDTH-1:0]] };
  
  assign empty = oldwraddr[DFFADDRWIDTH:0] == rdaddr[DFFADDRWIDTH:0];
  assign full = (wraddr[DFFADDRWIDTH-1:0] == rdaddr[DFFADDRWIDTH-1:0]) &&
                (wraddr[DFFADDRWIDTH] != rdaddr[DFFADDRWIDTH]);
  
 /* wire dmareq  =  (oldwraddr[DFFADDRWIDTH:0] == rdaddr[DFFADDRWIDTH:0]) || ( (oldwraddr[DFFADDRWIDTH-1:0] == DISDMA)
				  && (rdaddr[DFFADDRWIDTH-1:0] == ENADMA || rdaddr[DFFADDRWIDTH-1:0] == ENADMA1 ) ) ; */
  
  
  wire dffrdready = ~empty;
  wire dffwrready = ~full;

endmodule