usbmmc.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : usbmmc 
#     
#    Revision     : $Revision: 1.60 $
#    
#---------------------------------------------------------------------------
#   Purpose : USB to MMC interface.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module usbmmc	(
		// input
                sof,
                setcmdwr,
		usb_48_clock_uf_in,
                divide_rate,
		usb_clock_uf_in,
                mmc_enable,
		sync_reset_uf_in,
                spimode,
		dataout_dat_in,
		dataout_dat_out,
		dataout_dat_enable,
                getstatus,
                getstatus_check,
                getdata,
//                cs1_in,
//                cs2_in,
                clock_5m,

		cmdrdready_uf_in,
		cmdrddata_uf_in,

		endp1rdready_uf_in,
		endp1rddata_uf_in,
		
                statuswrready_uf_in,
		endp2wrready_uf_in,

		// output
                clock_5m_out,
		cmdrd_fu_out,
                cmdrddatadone_fu_out,

		statuswr_fu_out,
		statuswrdata_fu_out,
                statuswrdatadone_fu_out,

		endp1rd_fu_out,
		endp1rddatadone_fu_out,

		endp2wr_fu_out,
		endp2wrdata_fu_out,
		endp2wrdatadone_fu_out,

//////////////////
                cs_fc_out,
                status_receive_1,
                data_receive_1,
//////////////////
//		cs1_rsv,
//		cs2_rsv,
		clock_fc_out,
		datain_cmd_in,
		datain_cmd_out,
		datain_cmd_enable,
                sync_reset_made,
                busy_end_out,
                endp3,
//                endp3flag,
                data_in,
                clk_mcu,
                data_out
		);
	
//	hardware structure
//	usb core(u) - mmc interface(f) - mmc card(c)
//	signal from usb core to mmc interface "_uf"
//	signal to usb core from mmc interface "_fu"
//	signal from mmc interface to mmc card "_fc"
//	signal to mmc interface from mmc card "_cf"

// variable notation : 	variable's postfix of input to usbmmc "_in"
//			variable's postfix of output from usbmmc "_out"			
// 			

input                 data_in;
output                clk_mcu;
output                data_out;
/////////////
output                cs_fc_out;
output                status_receive_1;
output                data_receive_1;
////////////
input			usb_48_clock_uf_in;
input    [`THREE:`LSB]  divide_rate;
input			usb_clock_uf_in;
input                   mmc_enable;
input			sync_reset_uf_in;
input                   spimode;
input                   setcmdwr;
input                   sof;

input			dataout_dat_in;
output			dataout_dat_out;
output			dataout_dat_enable;

input                   getstatus;
input                   getstatus_check;
input                   getdata;
//input                   cs1_in;
//input                   cs2_in;

input			cmdrdready_uf_in;
input	[`BYTE:`LSB]	cmdrddata_uf_in;

input			endp1rdready_uf_in;
input	[`BYTE:`LSB]	endp1rddata_uf_in;

input                   statuswrready_uf_in;
input			endp2wrready_uf_in;
input           clock_5m;
output  [15:`LSB] endp3;
//output                 endp3flag;
//output                  cs1_rsv;
//output                  cs2_rsv;
output                  clock_5m_out;
output			cmdrd_fu_out;
output			cmdrddatadone_fu_out;

output			statuswr_fu_out;
output	[`BYTE:`LSB]	statuswrdata_fu_out;
output			statuswrdatadone_fu_out;

output			endp1rd_fu_out;
output			endp1rddatadone_fu_out;

output			endp2wr_fu_out;
output	[`BYTE:`LSB]	endp2wrdata_fu_out;
output			endp2wrdatadone_fu_out;

output			clock_fc_out;
input			datain_cmd_in;
output			datain_cmd_out;
output			datain_cmd_enable;

output			sync_reset_made;
output                  busy_end_out;

reg                     cs_fc_out;
reg                     data1_fc_out;
reg                     data2_fc_out;
reg                     cmd_transmit_1;
reg                     data_transmit_1;
reg                     status_receive_1;
reg                     data_receive_1;
//reg                     cs1_out;
//reg                     cs2_out;


//wire			datain_cmd;
		
wire			clock_fc_out;
wire			clock_5m;
wire			transmit;
wire			cmd_pre_transmit;
wire                    active_cs;
wire                    sync_reset_made;
wire                    status_cf_in;
wire                    dat_cf_in;
wire                    status_receive;
wire			data_receive;
wire                    tmp_multi_getdata;

//assign                  endp3flag = &endp3;
gen_clock_5m u0_gen_clock_5m( 
                              .usb_48_clock_uf_in(usb_48_clock_uf_in),
                              .usb_clock_uf_in(usb_clock_uf_in),
                              .divide_rate(divide_rate),
                              .sync_reset_uf_in(sync_reset_uf_in),
                              .sync_reset_made(sync_reset_made),
                              .clock_5m(clock_5m_out)
                             );
cmd_transmit u0_cmd_transmit (
                // input
                .mmc_enable(mmc_enable),
                .clock_5m(clock_5m),
                .sync_reset_uf_in(sync_reset_made),

                .cmdrdready_uf_in(cmdrdready_uf_in),
                .cmdrddata_uf_in(cmdrddata_uf_in),
                .tmp_multi_getdata(tmp_multi_getdata),

                // output
                .cmdrd_fu_out(cmdrd_fu_out),
                .cmdrddatadone_fu_out(cmdrddatadone_fu_out),

                .cmd_transmit(cmd_transmit),
                .cmd_fc_out(cmd_fc_out),
                .cmd_pre_transmit(cmd_pre_transmit)
                      );
data_transmit u0_data_transmit (
                // input
                .setcmdwr(setcmdwr),
                .mask_transmit(mask_transmit),
                .mmc_enable(mmc_enable),
                .clock_5m(clock_5m),
                .sync_reset_uf_in(sync_reset_made),

                .endp1rdready_uf_in(endp1rdready_uf_in),
                .endp1rddata_uf_in(endp1rddata_uf_in),

                // output
                .endp1rd_fu_out(endp1rd_fu_out),
                .endp1rddatadone_fu_out(endp1rddatadone_fu_out),

                .tmp_multi_getdata(tmp_multi_getdata),
                .multi_getdata(multi_getdata),

                .data_transmit(data_transmit),
                .dat_fc_out(dat_fc_out)
                      );
status_receive u0_status_receive (
                // input
                .tmp_multi_getdata(tmp_multi_getdata),
                .mmc_enable(mmc_enable),
                .clock_5m(clock_5m),
                .sync_reset_uf_in(sync_reset_made),
                .dat_cf_in(dat_cf_in),
                .status_cf_in(status_cf_in),
                .spimode(spimode),
                .sof(sof),

                .getstatus_in(getstatus),
                .getstatus_check(getstatus_check),
                .statuswrready_uf_in(statuswrready_uf_in),  // needless signal ????
                .cmdrddatadone_fu_out(cmdrddatadone_fu_out),

                // output
                .statuswr_fu_out(statuswr_fu_out),
                .statuswrdata_fu_out(statuswrdata_fu_out),
                .statuswrdatadone_fu_out(statuswrdatadone_fu_out),

                .busy_end_out(busy_end_out),
                .status_busy_check(status_busy_check),
		.status_receive(status_receive)
                      );
data_receive   u0_data_receive (
                // input
                .sof(sof),
                .multi_getdata(multi_getdata),
                .setcmdwr(setcmdwr|multi_getdata),
                .mmc_enable(mmc_enable),
                .clock_5m(clock_5m),
                .sync_reset_uf_in(sync_reset_made),
                .dat_cf_in(dat_cf_in),
                .spimode(spimode),
                .getdata(getdata|multi_getdata),
                .divide_rate(divide_rate),

                .data_transmit (data_transmit),

                .endp2wrready_uf_in(endp2wrready_uf_in),
                .cmdrddatadone_fu_out(cmdrddatadone_fu_out),
                .endp1rddatadone_fu_out(endp1rddatadone_fu_out),

                // output
                .mask_clock(mask_clock),
                .mask_transmit(mask_transmit),
                .endp2wr_fu_out(endp2wr_fu_out),
                .endp2wrdata_fu_out(endp2wrdata_fu_out),
                .endp2wrdatadone_fu_out(endp2wrdatadone_fu_out),

                .endp3(endp3),
		.data_receive(data_receive)
                      );

assign clock_fc_out = (!cs_fc_out && !mask_clock)? clock_5m : `HIGH;
assign clk_mcu = clock_fc_out & spimode;
assign active_cs = cmd_transmit || cmd_pre_transmit || data_transmit || status_receive || data_receive || status_busy_check;

always @(posedge clock_5m)
	if(sync_reset_made) cs_fc_out <= `HIGH;
	   else cs_fc_out <= !active_cs;

///////////////// must be erased when integrating with top module. 
always @(posedge clock_5m)
  begin   
    status_receive_1 <= status_receive;
    data_receive_1 <= data_receive;
  end
////////////////////////////////

/*
always @(posedge clock_5m)
  begin
    cs1_out <= cs1_in;
    cs2_out <= cs2_in;
  end
*/

always @(negedge clock_5m)
  if(sync_reset_uf_in) data1_fc_out <= `DEFAULT_DATA_OUT;
    else if(cmd_transmit) data1_fc_out <= cmd_fc_out;
             else data1_fc_out <= `HIGH;

always @(negedge clock_5m)
  if(sync_reset_uf_in) data2_fc_out <= `DEFAULT_DATA_OUT;
    else if(data_transmit) data2_fc_out <= dat_fc_out;
             else data2_fc_out <= `HIGH;

//assign cs1_rsv = (spimode)? cs1_out : `HIGH;
//assign cs2_rsv = (spimode)? cs2_out : `HIGH;
    
always @(negedge clock_5m)
  begin
  cmd_transmit_1 <= cmd_transmit;
  data_transmit_1 <= data_transmit;
  end

//assign datain_cmd_enable = !(spimode | (!spimode & cmd_transmit_1));
assign datain_cmd_enable = !(!spimode & cmd_transmit_1);
//assign datain_cmd_out = (spimode)? (data1_fc_out&& data2_fc_out) :
assign data_out = (spimode)? (data1_fc_out&& data2_fc_out) : `HIGH;
assign datain_cmd_out = (spimode)? `HIGH :
                        (cmd_transmit_1)? data1_fc_out : `HIGH;

assign dataout_dat_enable = !(!spimode & data_transmit_1);
assign dataout_dat_out = (!dataout_dat_enable)? data2_fc_out : `HIGH;

//assign datain_cmd = (spimode)? (data1_fc_out&& data2_fc_out) : 
//                    (cmd_transmit_1)? data1_fc_out : 1'bz; 
//assign dataout_dat = (spimode)? 1'bz : 
//                     (data_transmit_1)? data2_fc_out : 1'bz; 

//assign status_cf_in =(spimode)? dataout_dat_in : datain_cmd_in;
assign status_cf_in =(spimode)? data_in : datain_cmd_in;
assign dat_cf_in = dataout_dat_in;

endmodule