uctlreg.v

实现USB接口功能的VHDL和verilog完整源代码

// This module have a register bank for storing Commands and Cards Status

module UCtlreg (
				// USB
				getbusy,
				getstatus,
				usbclock,
				syncreset,
				mcclock,
				mcreset,
				cmdwrusb,
				statusrdusb,
				getstatuscheck,
				cmddatausb,
				statusdatausb,
				statusrdreadyusb,
				cmdwrreadyusb,
				datapacketok,
				datapacketnotok,
				// M/C 
                cmdrdmc,
				cmddatamc,
				statuswrmc,
				statusdatamc,
                statuswrreadymc,
                cmdrdreadymc,
				// configuration of MMC or SSFDC
				enmmc
				);
input       getbusy;
input       getstatus;
input       usbclock;
input       syncreset;
input       mcclock;
input       mcreset;
input       datapacketok;
input       datapacketnotok;
input       getstatuscheck;
input       cmdwrusb;
input       statusrdusb;
input [7:0] cmddatausb;
input       enmmc;

output[7:0] statusdatausb;
output statusrdreadyusb;
output cmdwrreadyusb;
input  cmdrdmc;
output [7:0] cmddatamc;
input  statuswrmc;
input[7:0] statusdatamc;

output statuswrreadymc;
output cmdrdreadymc;

reg[3:0] cwraddr, crdaddr , oldcwraddr; 
reg[3:0] swraddr, srdaddr, oldsrdaddr;

reg[7:0]  cmdreg[6:0];

reg[7:0]  statusreg[6:0];

reg       cmdrdreadymc;
reg       statusrdreadyusb;

wire[2:0] CFULL = 3'b111;
//wire[2:0]    CFULL = (enmmc) ? 3'b111 : 3'b111; 
wire  maskaddr = (enmmc) ? (getstatus || getstatuscheck) : getstatus || getbusy ;
always@(posedge usbclock)
 begin
	  if(syncreset)
        begin
		cwraddr <='h0;
		oldcwraddr <='h0;
        end
      else 
		 begin
    		  cmdreg[cwraddr[2:0]] <= (cmdwrusb) ? cmddatausb : cmdreg[cwraddr[2:0]];
    		  cwraddr <= (cmdwrusb) ? cwraddr +1 :( (datapacketnotok) ? oldcwraddr:
    		  			 (cwraddr[2:0] == CFULL) ? { ~cwraddr[3],3'b000 } : cwraddr);
			  oldcwraddr <= (datapacketok)? cwraddr : oldcwraddr;
		  end
 end

always@(posedge mcclock)
 begin
	if(mcreset)
      crdaddr <= 'h0;		 
	else if ( cmdrdmc ) 
      crdaddr <= crdaddr + 1;		 
	else if ( crdaddr[2:0] == CFULL ) 
      crdaddr <= {~crdaddr[3],3'b000} ;
	 //crdaddr <= (cmdrdmc)? crdaddr +1 : ((crdaddr[2:0] == CFULL) ? {~crdaddr[3],3'b000} : crdaddr);
 end

wire[7:0] cmddatamc = cmdreg[crdaddr[2:0]];
wire cempty = oldcwraddr[3:0] == crdaddr[3:0];
wire cfull = (cwraddr[2:0] == crdaddr[2:0]) && (cwraddr[3] != crdaddr[3]);

always@(posedge mcclock)
	cmdrdreadymc <=  cempty ? 0 : (cfull? 1: cmdrdreadymc);

reg cmdwrreadyusb;
always@(posedge usbclock)
   cmdwrreadyusb <= cempty ? 1 : (cfull ? 0 : cmdwrreadyusb);

//wire cmdwrreadyusb = ~cmdrdreadymc;

//wire[2:0]  SFULL = (enmmc) ? 3'b111 :3'b011;
wire  SFULL = (enmmc) ? 1'b1 :1'b0;

//wire[2:0]  SFULL = (enmmc) ? 3'b011 : 2'b10;

always@(posedge usbclock)
 begin
     if(syncreset || !maskaddr)
		begin
		  srdaddr <='h0;
          oldsrdaddr <='h0;
        end
     else
	   begin
		  srdaddr <=(statusrdusb) ? srdaddr +1 : ( (datapacketnotok) ? oldsrdaddr:
					 (srdaddr[2:0] == {SFULL,2'b11} ) ? { ~srdaddr[3],3'b000} : srdaddr);
					 
          oldsrdaddr <=(datapacketok) ? srdaddr : oldsrdaddr;
       end
end

always@(posedge mcclock)
  begin
	  if(mcreset || !maskaddr)
		 swraddr <='h0;
      else
		begin
		 statusreg[swraddr[2:0]] <= (statuswrmc) ? statusdatamc : statusreg[swraddr[2:0]];
		 swraddr <=(statuswrmc) ? swraddr +1 :( (swraddr[2:0] == {SFULL,2'b11}) ? {~swraddr[3],3'b000} 
					:swraddr);
		 end
  end

wire[7:0] statusdatausb = statusreg[srdaddr[2:0]];
wire      sempty    = oldsrdaddr[3:0] == swraddr[3:0];
//wire      sfull     = (srdaddr[1:0] == swraddr[1:0]) && (srdaddr[2] != swraddr[2]);
wire      sfull = (swraddr[2:0] == {SFULL,2'b11} ) ;//&& (srdaddr[2] != swraddr[2]);
reg statuswrreadymc;

always@(posedge usbclock)
 begin
    statusrdreadyusb <= ~ statuswrreadymc;
 end
 always@(posedge mcclock)
    statuswrreadymc <= sempty ? 1 : (sfull ? 0 : statuswrreadymc );  


endmodule