usbtop.v

实现USB接口功能的VHDL和verilog完整源代码

// THIS BLOCK INCLUDES 8051IF 

module Usbtop
	(
	// inputs from bus
		pwronreset,
		clock48,	// 48 MHz clock
		rcvin,		// differential in
		vpin,		// plus in
		vmin,		// minus in
		vmo,		// minus out
		vpo,		// plus out
		usboen,	// oe for usb bits
		suspend
	);
  
  input     pwronreset;
  input	     clock48;
  input	     rcvin;
  input	     vpin;
  input	     vmin;
  output     vmo;
  output     vpo;
  output     usboen;
  output     suspend;

// wires for endpoints
  wire	     endp0rdstall = 1'b0;
  wire	     endp0wrstall = 1'b0;
  wire	     endp1wrstall = 1'b0;
 
 
  wire [7:0] currentalternatesetting;
  wire [7:0] endpwrdata;
  wire [7:0] endp2rddata;
  wire [7:0] endp0rddata;
  wire [6:0] devromdescriptorindex;
  wire [7:0] devromsetupaddr;
  wire [7:0] romdevsetupdata;
  wire [2:0] setupbyteaddr = 3'b000;
  wire [7:0] setupdataout;	// one of 8 bytes of the setup stage data
  wire[10:0] framenumber;

Ucore core (
        .clock48 (clock48),
        .rcvin (rcvin),
        .vpin (vpin),
        .vmin (vmin),
        .vmo (vmo),
        .vpo (vpo),
        .usboen (usboen),
        .usbclockout (usbclock),
        .usbclock (usbclock),
        .pwronreset(pwronreset),
	    .usbreset (usbreset),
	    .endpwrdata (endpwrdata),
	    .datapacketok (datapacketok),
	    .datapacketnotok (datapacketnotok),
        .devromdescriptorindex(devromdescriptorindex),
        .devromsetupaddr(devromsetupaddr),
        .romdevsetupdata(romdevsetupdata),
	    .romen(romen),
	    .endp0internaltogglebit(endp0internaltogglebit),
        .setupcycle(setupcycle),
        .setupbyteaddr(setupbyteaddr),
        .setupdata(setupdataout),
	    .rcvack(rcvack),
	    .suspend(suspend),
		.framenumber(framenumber),
		.currentalternatesetting (currentalternatesetting),
    
	// Vendor CMD Decoding
		.getstatus(getstatus),
		.setcmd(setcmd),
	// connections to endpoint0 - read/write
	.endp0wr (endp0wr),
	.endp0wrready (endp0wrready),
	.endp0wrstall (endp0wrstall),
	.endp0rd (endp0rd),
	.endp0rddata (endp0rddata),
	.endp0rdready (1'b1),
	//.endp0rdready (endp0rdready),
	.endp0rdstall (endp0rdstall),

	// connections to endpoint1 - write only
	.endp1wr (endp1wr),
	.endp1wrready (endp1wrready),
	.endp1wrstall (endp1wrstall),

	// connections to endpoint2 - read only
	.endp2rd (endp2rd),
	.endp2rddata(endp2rddata),
	.endp2rdready(endp2rdready),
	.endp2rdstall (endp2rdstall)
	);

Udevrom rom (
	// addressing
	.devromdescriptorindex (devromdescriptorindex),
	.devromsetupaddr (devromsetupaddr),

	// read port
	.romdevsetupdata (romdevsetupdata)
	);

	       
endmodule