ubulkfifotx.v

实现USB接口功能的VHDL和verilog完整源代码

//`timescale 1ns / 100ps
module Ubulkfifotx (
		syncreset, 
		 BCLK,
		 usbclock,
		 dff2wr,
		 dff2rd,
		 dff2wrdata,
		 dff2rddata,
		 dff2rdready,
		 dff2wrready,
		 datapacketok,
//		 dmareqtx,
		 datapacketnotok
		 );
  input          syncreset; 
  input         BCLK;
  input			 usbclock;
  input			 dff2wr;
  input			 dff2rd;
  parameter	 DFFDEPTH = 32,
			 DMAWIDTH =32,
			 DFFWIDTH = 8,
		//	 ENADMA =24, //8
		//	 ENADMA1=28, //28
		//	 DISDMA =0,
			 DFFADDRWIDTH = 5;	// 2^6 is 64
 
  input [31:0]	 dff2wrdata;
  output [DFFWIDTH-1:0] dff2rddata;
  output		 dff2rdready;
  output		 dff2wrready;
 // output         dmareqtx;
  input			 datapacketok;
  input			 datapacketnotok;

  reg [DFFWIDTH-1:0]	 ffdata [DFFDEPTH-1:0];
  reg [DFFADDRWIDTH:0] wraddr,rdaddr,oldrdaddr;
  reg                    rdok;
  reg                    ord1, ord2;
  reg            dmareqtx;

  wire			 full,empty;
  wire                   pok = (datapacketok && (rdok != rdaddr[DFFADDRWIDTH]) &&
                                (ord2 != rdaddr[DFFADDRWIDTH])); 
  wire                   pnok = (datapacketnotok && (rdok != rdaddr[DFFADDRWIDTH]) &&
                                 (ord2 != rdaddr[DFFADDRWIDTH])); 

  always @(posedge usbclock or posedge syncreset)
    begin
      if (syncreset)
      	   begin
	       rdaddr <= 'h0;
	       oldrdaddr <= 'h0;
	      end // if (asyncreset)
      else
	       begin
          rdaddr <= (dff2rd) ? rdaddr + 1'b1 : rdaddr;
		   oldrdaddr[DFFADDRWIDTH] <= pok ? wraddr[DFFADDRWIDTH] : pnok ? 
            ~wraddr[DFFADDRWIDTH] : oldrdaddr[DFFADDRWIDTH];
           ord1 <= oldrdaddr[DFFADDRWIDTH];
           ord2 <= ord1;
		   end
    end // always @ (posedge usbclock)
  
  always @(posedge dff2rd or posedge syncreset)
    begin
      if(syncreset)
        rdok <= 'h0;
      else 
        rdok <= rdaddr[DFFADDRWIDTH];
    end

   
  always @(posedge BCLK or posedge syncreset ) 
   begin
	  if(syncreset)
	   wraddr <= 'h0; 
        
		else if (dff2wr) 
		      wraddr <= wraddr + 4;
        
    end
wire[4:0] test1 = wraddr[DFFADDRWIDTH -1:0] -1;
wire[4:0] test2 = wraddr[DFFADDRWIDTH -1:0] -2;
wire[4:0] test3 = wraddr[DFFADDRWIDTH -1:0] -3;
wire[4:0] test4 = wraddr[DFFADDRWIDTH -1:0] -4;

    always @(negedge BCLK)
	begin
	   if(dff2wr)  begin

     			ffdata[test4] <= dff2wrdata[31:24];
	    	    ffdata[test3] <= dff2wrdata[23:16];
	    		ffdata[test2] <= dff2wrdata[15:8];
	    	    ffdata[test1] <= dff2wrdata[7:0];
                end
    end
  
  wire [DFFWIDTH-1:0] dff2rddata = ffdata[rdaddr[DFFADDRWIDTH-1:0]];

  assign empty = (wraddr[DFFADDRWIDTH] == oldrdaddr[DFFADDRWIDTH]);
  assign full  = (wraddr[DFFADDRWIDTH] != oldrdaddr[DFFADDRWIDTH]); 
 /* wire  dmareq =( ( wraddr[DFFADDRWIDTH-1:0] ==ENADMA || wraddr[DFFADDRWIDTH-1:0] == ENADMA1) && (oldrdaddr[DFFADDRWIDTH-1:0] ==DISDMA)) ||
				 (wraddr[DFFADDRWIDTH] != oldrdaddr[DFFADDRWIDTH]) ; */
					
 /* 

  always@(negedge BCLK)
	  dmareqtx = dmareq;
                          */
  wire dff2rdready = ~empty;
  wire dff2wrready = ~full;
/*
  wire [DFFWIDTH-1:0] debugdata15 = ffdata[15];
  wire [DFFWIDTH-1:0] debugdata14 = ffdata[14];
  
  
  wire [DFFWIDTH-1:0] debugdata13 = ffdata[13];
  wire [DFFWIDTH-1:0] debugdata12 = ffdata[12];
  wire [DFFWIDTH-1:0] debugdata11 = ffdata[11];
  wire [DFFWIDTH-1:0] debugdata10 = ffdata[10];
  wire [DFFWIDTH-1:0] debugdata9 = ffdata[9];
  wire [DFFWIDTH-1:0] debugdata8 = ffdata[8];
  wire [DFFWIDTH-1:0] debugdata7 = ffdata[7];
  wire [DFFWIDTH-1:0] debugdata6 = ffdata[6];
  wire [DFFWIDTH-1:0] debugdata5 = ffdata[5];
  wire [DFFWIDTH-1:0] debugdata4 = ffdata[4];
  wire [DFFWIDTH-1:0] debugdata3 = ffdata[3];
  wire [DFFWIDTH-1:0] debugdata2 = ffdata[2];
  wire [DFFWIDTH-1:0] debugdata1 = ffdata[1];
  wire [DFFWIDTH-1:0] debugdata0 = ffdata[0];
*/
endmodule