pll
锁相环(PLL: Phase-locked loops)是一种利用反馈控制原理实现的频率及相位的同步技术，其作用是将电路输出的时钟与其外部的参考时钟保持同步。当参考时钟的频率或相位发生改变时，锁相环会检测到这种变化，并且通过其内部的反馈系统来调节输出频率，直到两者重新同步，这种同步又称为“锁相”
pll 全部资料 214 份
PhD.thesis about fractional PLL design from UC san-deago.
PhD.thesis about fractional PLL design from UC san-deago....
MC33493 - PLL tuned UHF Transmitter for Data Transfer Applications - Motorola, Inc
MC33493 - PLL tuned UHF Transmitter for Data Transfer Applications - Motorola, Inc...
基于VXI总线用DDS+PLL技术实现精密时钟源
DDS（直接数字频率合成）技术是一门在频率合成领域的新兴技术，具有响应时间短，精度高等优点。而PLL（Phase Locked Loop）锁相环技术虽然工作速度慢，但稳定可靠。VXI 总线具有...
04 calgary PhD Improving Tracking Performance of PLL in High Dynamic Applications.pdf
资料->【E】光盘论文->【E1】斯坦福博士论文->04 calgary PhD Improving Tracking Performance of PLL in High Dynamic Appli...
Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides
Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides...