boothcode.v

ＦＰＧＡ实现数字滤波器

module boothcode(ai,bi,b0,b1,b2,b3);
    input[7:0] ai;
    input[8:0] bi;
    output[15:0] b0,b1,b2,b3;  
    wire[15:0] b0,b1,b2,b3;     
    wire[9:0] b10,b321,b543,b765;
     
function[9:0] booth; 
input a,b,c;              
input[8:0] d;        
case({a,b,c})             
    3'b000:booth=0;      
    3'b001:booth=d;          
    3'b010:booth=d;          
    3'b011:booth=d<<1;       
    3'b100:booth=~(d<<1)+1; 
    3'b101:booth=~(d)+1;      
    3'b110:booth=~(d)+1;     
    3'b111:booth=0;
    default:booth=0;
endcase          
endfunction    
           
     
     assign b10=booth(ai[1],ai[0],0,bi);
     assign b321=booth(ai[3],ai[2],ai[1],bi); 
     assign b543=booth(ai[5],ai[4],ai[3],bi); 
     assign b765=booth(ai[7],ai[6],ai[5],bi);
     
     assign b0[15:10]={6{b10[9]}};
     assign b0[9:0]=b10;
     assign b1[15:12]={4{b321[9]}};
     assign b1[11:0]=b321<<2;
     assign b2[15:14]={2{b543[9]}};
     assign b2[13:0]=b543<<4; 
     assign b3=b765<<6;
     
endmodule