fir_control.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 23 行

module fir_control(clk1,clk2,clrn,reset,oe,sel);
	input clk1,clk2,clrn;
	output [2:0] sel;
    output reset,oe;
	reg [1:0] state;
    reg [2:0] sel;
    reg  reset,oe;
	parameter 	Swait0=2'b00,S0=2'b01,S1=2'b10,Swait1=2'b11;
always @ (posedge clk2 or negedge clrn)
	if (!clrn)  begin state=Swait0;oe=0;sel=0;reset=0;end
	else   	
	case (state)
    	  Swait0:  if (!clk1) begin oe=0;sel=0;reset=0;end
                else begin state=S0;oe=0;reset=1;end
	    S0: if(sel<7)  begin sel=sel+1;reset=1;oe=0;end
                else begin  state=S1;reset=1;oe=1;end
	    S1: if(clk1) begin state=Swait1;oe=0 ; end
                else begin state=Swait0;oe=0;sel=0;reset=0;end
	    Swait1: if (!clk1) begin  state=Swait0;oe=0;sel=0;reset=0;end
            default :begin  state=Swait0;oe=0;sel=0;reset=0;end
     endcase   	
endmodule