mux8_1.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 21 行

module mux8_1(sel,h0,h1,h2,h3,h4,h5,h6,h7,hi);
    input[7:0] h0,h1,h2,h3,h4,h5,h6,h7;
    input[2:0] sel;
    output[7:0] hi;
    reg[7:0] hi;
    
    always @(sel or h0 or h1 or h2 or h3 or h4 or h5 or h6 or h7)
    begin    
    case(sel)
        3'b000:hi=h0;
        3'b001:hi=h1;
        3'b010:hi=h2;
        3'b011:hi=h3;
        3'b100:hi=h4;
        3'b101:hi=h5;
        3'b110:hi=h6;
        3'b111:hi=h7;
        default:hi=0;
endcase
end
endmodule