adder8.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 22 行

module adder8(sum,cout,a,b,cin);
    input[7:0] a,b;
    input cin;
    output[7:0] sum;
    output cout;
    wire[7:0] sum;
    wire cout;
    wire cout0,cout1,cout2;
    wire[3:0] sum1,sum2;
    
    adder4 myadder8_40(sum[3:0],cout0,a[3:0],b[3:0],cin);
    adder4 myadder8_411(sum1,cout1,a[7:4],b[7:4],1);
    adder4 myadder8_410(sum2,cout2,a[7:4],b[7:4],0);
    assign sum[7:4]=cout0?sum1:sum2;
    assign cout=(cout0|cout2)&cout1;
endmodule