adder4.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 25 行

module adder4(sum,cout,a,b,cin);
    input[3:0] a,b;
    input cin;
    output[3:0] sum;
    output cout;
    wire[3:0] sum;
    wire cout;
    wire[3:0] g,p;
    wire c0,c1,c2,c3;
    
    assign g=a&b;
    assign p=a|b;
        
    assign c0=g[0]|(p[0]&cin);
    assign c1=g[1]|(p[1]&g[0])|(p[1]&p[0]&cin);
    assign c2=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin);
    assign c3=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&cin);
    
    assign sum[0]=p[0]&(~g[0])^cin;
    assign sum[1]=p[1]&(~g[1])^c0;
    assign sum[2]=p[2]&(~g[2])^c1;
    assign sum[3]=p[3]&(~g[3])^c2; 
    assign cout=c3;
        
endmodule