adderbu.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 17 行

module adderbu(a8,b8,a_b);
    input[7:0] a8,b8;
    output[8:0] a_b;
    wire[8:0] a_b;
    wire cout,c0;
     
    adder8 myadd(a_b[7:0],c0,a8,b8,0);
    assign {cout,a_b[8]}=a8[7]+b8[7]+c0;  
    
endmodule