adder16.v

来自「ＦＰＧＡ实现数字滤波器」· Verilog 代码 · 共 20 行

  module adder16(sum,cout,a,b,cin);
    input[15:0] a,b;
    input cin;
    output[15:0] sum;
    output cout;
    wire[15:0] sum;
    wire cout;
    wire cout0,cout1,cout2;
    wire[7:0] sum1,sum2;
    
    adder8 myadder16_0(sum[7:0],cout0,a[7:0],b[7:0],cin);
    adder8 myadder16_11(sum1,cout1,a[15:8],b[15:8],1);
    adder8 myadder16_10(sum2,cout2,a[15:8],b[15:8],0);
    assign sum[15:8]=cout0?sum1:sum2;
    assign cout=(cout0|cout2)&cout1;
endmodule