fir.v

ＦＰＧＡ实现数字滤波器

module fir(clrn,clk1,clk2,x,h0,h1,h2,h3,h4,h5,h6,h7,y);
input clk1,clk2,clrn;
input[7:0] x;
input[7:0] h0,h1,h2,h3,h4,h5,h6,h7;
output[15:0] y;
wire[15:0] y,yout;
wire reset,oe,clr;
wire[2:0] sel;
wire[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,xi,xn_i_1;
wire[8:0] a_b,bi;
wire[7:0] hi,a8,b8,ai;
wire[15:0] a,b,c,d,b0,b1,b2,b3;
wire[17:0] sum,hxi;
wire[20:0] hxin,hout,pout;


fir_control fircontrol(.clk1(clk1),.clk2(clk2),.clrn(clrn),.reset(reset),.oe(oe),.sel(sel));
shift firshift(.clk1(clk1),.x(x),
               .x0(x0),.x1(x1),.x2(x2),.x3(x3),
               .x4(x4),.x5(x5),.x6(x6),.x7(x7),
               .x8(x8),.x9(x9),.x10(x10),.x11(x11),
               .x12(x12),.x13(x13),.x14(x14),.x15(x15),
               .clr(clrn));
mux16_2 fir16mux(.sel(sel),.x0(x0),.x1(x1),.x2(x2),.x3(x3),
               .x4(x4),.x5(x5),.x6(x6),.x7(x7),
               .x8(x8),.x9(x9),.x10(x10),.x11(x11),
               .x12(x12),.x13(x13),.x14(x14),.x15(x15),
               .xi(xi),.xn_i_1(xn_i_1));
adderbu firadderbu(.a8(xi),.b8(xn_i_1),.a_b(a_b));
mux8_1 fir8mux(.sel(sel),.h0(h0),.h1(h1),.h2(h2),.h3(h3),.h4(h4),.h5(h5),.h6(h6),.h7(h7),.hi(hi));
boothcode firboothcode(.ai(hi),.bi(a_b),.b0(b0),.b1(b1),.b2(b2),.b3(b3));
wallace firwallace(.a(b0),.b(b1),.c(b2),.d(b3),.sum(sum));
alu firalu(.hxi(sum),.hxin(pout),.hout(hout));
trigger1 firtrigger1(.clk2(clk2),.reset(reset),.hout(hout),.pout(pout));
trigger2 firtrigger2(.oe(oe),.pout(pout),.yout(y));

endmodule