fir_tp.v

ＦＰＧＡ实现数字滤波器

`timescale 1ns/10ps
module fir_tp;
 reg clk1,clk2,clrn;
reg[7:0] x;
reg[7:0] h0,h1,h2,h3,h4,h5,h6,h7;
wire[15:0] y,yout;
wire reset,oe,clr;
wire[2:0] sel;
wire[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,xi,xn_i_1;
wire[8:0] a_b,bi;
wire[7:0] hi,a8,b8,ai;
wire[15:0] a,b,c,d,b0,b1,b2,b3;
wire[17:0] sum,hxi;
wire[20:0] hxin,hout,pout;

parameter dely1=64000;
parameter dely2=62.5;
fir myfir(clrn,clk1,clk2,x,h0,h1,h2,h3,h4,h5,h6,h7,y);
always #(dely1/2) clk1=~clk1;
always #(dely2/2) clk2=~clk2;
initial begin clrn=0;clk1=0;clk2=0;x=0;h0=8'd0;h1=8'd0;h2=8'd2;h3=-8'd4;h4=8'd5;h5=-8'd1;h6=-8'd14;h7=8'd76;
#dely2 clrn=1;
#(dely1/2) x=8'd10;//x=8'd1
#dely1 x=8'd2;
#dely1 x=8'd3;
#dely1 x=8'd4;
#dely1 x=8'd5;
#dely1 x=8'd6;
#dely1 x=8'd7;
#dely1 x=8'd8;
#dely1 x=8'd9;
#dely1 x=8'd10;
#dely1 x=8'd11;
#dely1 x=8'd12;
#dely1 x=8'd13;
#dely1 x=8'd14;
#dely1 x=8'd15;
#dely1 x=8'd16;
#dely1 x=8'd0;
#(dely1*20) $stop;

end

endmodule