xorphd_tp.v

ＦＰＧＡ实现全数字锁相环

module xorphd_tp;
    reg fin,fout;
    wire se;
    parameter DELY=100; 
    xorphd myxorphd(fin,fout,se);   
    always #(DELY/2) fin=~fin;
    always #(DELY) fout=~fout;
    initial 
    begin fin=0;fout=0;    
    #(DELY*30) $stop;
end
endmodule