maichongjiajian_tp.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 19 行

`timescale 1ns/10ps
module maichongjiajian_tp;
reg IDCLOCK,INC,DEC,reset;
wire Y,IDOUT;
wire[2:0] state,next_state; 
parameter DELY=10;
maichongjiajian mypulseadd_sub(IDCLOCK,INC,DEC,reset,IDOUT);
always #(DELY/2) IDCLOCK=~IDCLOCK;
initial
begin IDCLOCK=0;reset=0;INC=0;DEC=0;
#DELY reset=1;
#(DELY*20) INC=1;
#DELY INC=0;
#(DELY*20) DEC=1;
#DELY DEC=0;
#(DELY*20)$stop;
end
endmodule