divfrequency64.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 19 行

module divfrequency64(//input
                       IDOUT,reset,
                       //output
                       fout);
    input IDOUT,reset;
    output fout;
    wire fout;
    reg[5:0] count;
  
    always @(posedge IDOUT or reset)
     begin if(!reset) count=0;
           else if(count==6'd63)  count=0;
           else count=count+1;
           
       end
       assign fout=count[5];
              
    endmodule