divfrequency8_tp.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 16 行

`timescale 1ns/10ps
module divfrequency8_tp;
    reg clk,reset;
    wire IDCLOCK;    
    wire[2:0] count;
   
parameter DELY=10;
divfrequency8 mycount(clk,reset,IDCLOCK);
always #(DELY/2) clk=~clk;
initial
begin clk=0;reset=0;
#DELY reset=1;
#(DELY*20) $stop;
end
endmodule