divfrequency64_tp.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 15 行

`timescale 1ns/10ps
module divfrequency64_tp;
reg IDOUT;
reg reset;
wire fout;
wire[5:0] count;
parameter DELY=10;
divfrequency64 mycount(IDOUT,reset,fout);
always #(DELY/2) IDOUT=~IDOUT;
initial
begin IDOUT=0;reset=0;
#DELY reset=1;
#(DELY*100) $stop;
end
endmodule