mokcounter_tp.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 18 行

`timescale 1ns/10ps
module moKcounter_tp;
    reg se,clk,reset; 
    reg[3:0] K;
    wire[16:0] kmode,count;                                            
    wire carry,borrow;
    parameter DELY=100;
moKcounter mycount(clk,se,K,reset,carry,borrow);
always #(DELY/2) clk=~clk;
initial
begin se=0;clk=0;reset=0;K=0;
#DELY reset=1;K=4;
#(DELY*100) se=1;
#(DELY*200)$stop;
end
endmodule