maichongjiajian.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 54 行

module maichongjiajian(//input
                       IDCLOCK,INC,DEC,reset,
                       //output
                        IDOUT);              
                                                
input IDCLOCK,INC,DEC,reset;                                          
output IDOUT;                                                       
reg Y;
wire IDOUT;                                                          
reg[2:0] state,next_state;                                            
parameter s0=3'b000,s1=3'b001,s2=3'b011,s3=3'b010,s4=3'b110,s5=3'b111;
                                                                      
always @(negedge IDCLOCK)                                             
begin if(!reset) state<=s0;                                          
        else  state<=next_state;                                              
end                                                                   
                                                                      
always @(state or INC or DEC)                                         
begin                                                                 
    case(state)                                                       
     s0: begin if(INC)  next_state<=s2;                               
               else if(DEC) next_state<=s3;                           
               else next_state<=s1;                                          
         end                                                          
     s1: begin if(INC) next_state<=s4;                                
               else if(DEC) next_state<=s5;                           
               else next_state<=s0;                                          
         end                                                          
     s2:next_state<=s1;                                               
     s3:next_state<=s1;                                               
     s4:next_state<=s0;                                               
     s5:next_state<=s0;                                               
     default:next_state<=s0;                                           
    endcase    
end                                                                   
                                                                      
always @(state)                                                       
 begin                                                                
  case(state)                                                         
   s0:Y=0;                                                            
   s1:Y=1;                                                            
   s2:Y=1;                                                            
   s3:Y=0;                                                            
   s4:Y=1;                                                            
   s5:Y=0;                                                            
   default:Y=0;                                                       
   endcase                                                         
 end
 
 assign IDOUT=Y&&IDCLOCK;
                                                 
 endmodule