dpll_tp.v

来自「ＦＰＧＡ实现全数字锁相环」· Verilog 代码 · 共 18 行

`timescale 1ns/10ps
module dpll_tp;
    reg fin,clk,reset;
    reg[3:0] K;
    wire fout,fc2;
    parameter DELY1=62.5;
    parameter DELY2=64000;
    always #(DELY1/2) clk=~clk;
    always #(DELY2/2) fin=~fin;
    dpll mydpll(clk,fin,reset,K,fout,fc2);
    initial 
    begin clk=0;fin=0;reset=0;K=0;
    #(DELY1*10) reset=1;K=4'd9;
    #(DELY2*10000) $stop;
end
endmodule