cputop.v

verilog语言写的简单八位处理器。有8个模块

//-------------------------------------------cputop.v?------------------
//`include"ram.v"
//`include"rom.v"
//`include"addr_decode.v"
//`include"cpu.v"
 

`timescale 1ns/100ps
`define PERIOD 100
module cputop;

reg reset_req,CLOCK;
integer test;
reg[(3*8):0]mnemonic;
reg[12:0] PC_ADDR,IR_ADDR;
wire[7:0]DATA;
wire[12:0]ADDR;
wire RD,WR,HALT,ram_sel,rom_sel;



cpu t_cpu(.CLK(CLOCK),.RESET(reset_req),.HALT(HALT),.RD(RD),.WR(WR),.ADDR(ADDR),.DATA(DATA));
ram t_ram (.ADDR(ADDR[9:0]),.READ(RD),.WRITE(WR),.ENA(ram_sel),.DATA(DATA));
rom t_rom(.ADDR(ADDR),.READ(RD),.ENA(rom_sel),.DATA(DATA));
addr_decode  t_addr_decode(.ADDR(ADDR),.ram_sel(ram_sel),.rom_sel(rom_sel));


initial  
    begin
      CLOCK=1;
$timeformat(-9,1,"ns",12);
display_debug_message;
sys_reset;
test1;
$stop;
test2;
$stop;
test3;
$stop;

end
 task  display_debug_message;
    begin

           $display("\n************************************************");
           $display("*  THE FOLLOWING DEBUG TASK ARE AVAILABLE:*");
           $display("*\"test1;\"to load the 1st diagnostic PTOGRAM.*");
           $display("*   \"test2;\"to load the 2nd diagnstic PROGRAM.*");
           $display("*   \"test3;\"to load the Fibonacci PROGRAM.*");
       	   $display("***************************************************************\n");
     end
  endtask
task test1;
    begin     
       test=0;
      disable MONITOR;
      $readmemb("test1.pro",t_rom.memory);
      $display("rom loaded    successfully!");
      $readmemb("test1.dat",t_ram.ram);
      $display("ram loaded    successfully!");
      #1 test=1;
      #14800 ;
      sys_reset;
    end
  endtask



task test2;

      begin
         test=0;
         disable MONITOR;
         $readmemb("test2.pro",t_rom.memory);
         $display("rom loaded   successfully!");
         $readmemb("test2.dat",t_ram.ram);
         $display("ram loaded   successfully!");
         #1 test=2;
         #11600;
        sys_reset;
      end 



endtask
task test3;
   begin
       test=0;
       disable MONITOR;
       $readmemb("test3.pro",t_rom.memory);
       $display("rom loaded successfully!");
       $readmemb("test3.dat",t_ram.ram);
       $display("ram loaded successfully!");
       #1 test=3;
       #94000;
       sys_reset;
   end
   endtask
   task sys_reset;
       begin
           reset_req=0;
           #(`PERIOD*0.7)reset_req=1;
           #(1.5*`PERIOD)reset_req=0;
       end
   endtask
   always@(test)
   begin:MONITOR
   case(test)
       1:begin
           $display("\n***RUNNING CPUtest1-The Basic CPU Diagnostic Program***");
           $display("\n TIME PC INSTR ADDR DATA");
           $display(" ----------      ---- -----    -----     -----");
           while (test==1)
              @(t_cpu.m_adr.PC_ADDR)
              if((t_cpu.m_adr.PC_ADDR%2==1)&&(t_cpu.m_adr.FETCH==1))
        begin
        #60 PC_ADDR<=t_cpu.m_adr.PC_ADDR-1;
        IR_ADDR<=t_cpu.m_adr.IR_ADDR;
        #340 $strobe("%t %h %s %h %h",$time,PC_ADDR,mnemonic,IR_ADDR,DATA);
    end
end

2:begin
$display("\n ***RUNNING CPUtest2-The advanced cpu diagnostic Program***");
$display("\n Time pc instr addr data");
$display("--------- --- ---- ----- ----");
while (test==2)
@(t_cpu.m_adr.PC_ADDR)
if((t_cpu.m_adr.PC_ADDR%2==1)&&(t_cpu.m_adr.FETCH==1))
   begin
    #60 PC_ADDR<=t_cpu.m_adr.PC_ADDR-1;
        IR_ADDR<=t_cpu.m_adr.IR_ADDR;
    #340 $strobe("%t %h %s %h %h",$time,PC_ADDR,mnemonic,IR_ADDR,DATA);
   end
end
3:begin
   $display("\n***running cputest3-an executable Program***");
   $display("***This Program should calculate the fibonacci***");
   $display("\n Time fibonacci number");
   $display("------- ------------");
   while (test==3)
      begin 
           wait(t_cpu.m_alu.OPCODE==3'h1)
           $strobe("%t %d", $time,t_ram.ram[10'h2]);
           wait(t_cpu.m_alu.OPCODE!=3'h1);
       end
    end
 endcase
 end
 always@(posedge HALT)
 begin
     #500
     $display("\n**********************************");
     $display("**a halt instruction was processed!!!***");
     $display("*************************************");
 end
 always#(`PERIOD/2) CLOCK=~CLOCK;
 always @(t_cpu.m_alu.OPCODE)
   case(t_cpu.m_alu.OPCODE)
       3'b000:mnemonic="HLT";
       3'h1  :mnemonic="SKZ";
       3'h2  :mnemonic="ADD";
       3'h3    :mnemonic="AND";
       3'h4    :mnemonic="XOR";
       3'h5   :mnemonic="LDA";
       3'h6   :mnemonic="STO";
       3'h7   :mnemonic="JMP";
       default: mnemonic="???";
   endcase
   endmodule