clock.v

使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.

module clock(clk,
             reset,
             dorjshift,
             jordshift,
             hmshift,
             msshift,
             judgepulse,
             display,
             ledshowst,
             sl1,
             sl2,
             sl3,
             sl4);

input clk,reset,dorjshift,jordshift,hmshift,msshift,judgepulse;
output sl1,sl2,sl3,sl4;
output[7:0] display;
output[2:0] ledshowst;

wire f1,f1k,outtosec,infmsec,outtomin,infmmin,outtohou;
//wire secsel,minsel,housel;
wire[7:0] secdata,mindata,houdata,datahigh,datalow;


//devfreq10hz hhz(clk,reset,f10);
devfreq1hz  hz(clk,reset,f1);
devfreq1khz khz(clk,reset,f1k);

qudou  qudou(.f1k(f1k),.reset(reset),.pulsein(judgepulse),.pulseout(qdpulse));

control control(.clk(clk),
                .reset(reset),
                .secdata(secdata),
			          .mindata(mindata),
			          .houdata(houdata),
                .freq1hz(f1),
                .infmsec(infmsec),
                .infmmin(infmmin),
             //   .secsel(secsel),
              //  .minsel(minsel),
              //  .housel(housel),
                .outtosec(outtosec),
                .outtomin(outtomin),
                .outtohou(outtohou),
                .hmshift(hmshift),
				        .msshift(msshift),
				        .dorjshift(dorjshift),
				        .jordshift(jordshift),
		          	.judgepulse(qdpulse),
                .ledshowst(ledshowst),
		         	  .datahigh(datahigh),
			          .datalow(datalow));
/*
mux2_1b  secosel(.out(outtosec),
                 .a(f1),
                 .b(0'b0),
                 .sel(secsel));
                 
mux2_1b  minusel(.out(outtomin),
                 .a(infmsec),
                 .b(judgepluse),
                 .sel(minsel));

mux2_1b  hoursel(.out(outtohou),
                 .a(infmmin),
                 .b(judgepluse),
                 .sel(housel));
*/               
count60 sec(.clk(outtosec),
            .reset(reset),
		        .out(secdata),
		        .cout(infmsec) );

count60 min(.clk(outtomin),
            .reset(reset),
		        .out(mindata),
		        .cout(infmmin) );

count12 hou(.clk(outtohou),
            .reset(reset),
		        .out(houdata));

display dis(.datalow(datalow),
            .datahigh(datahigh),
		        .freq1k(f1k),
		        .reset(reset),
            .displaydata(display),
	      	  .sl1(sl1),
	     	    .sl2(sl2),
		        .sl3(sl3),
	      	  .sl4(sl4));
                
endmodule