control.v

使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.

module control(clk,
               reset,
               secdata,
               mindata,
               houdata,
               freq1hz,
               infmsec,
               infmmin,
           //   secsel,minsel,housel,  
               outtosec,
               outtomin,
               outtohou,
               hmshift,
               msshift,
               dorjshift,
		     jordshift,
               judgepulse,
               ledshowst,
               datahigh,
               datalow);
               
input clk,reset,freq1hz,hmshift,msshift,dorjshift,jordshift,judgepulse,infmsec,infmmin;
input[7:0] secdata,mindata,houdata;
//output secsel,minsel,housel;
output[7:0] datahigh,datalow;
output[2:0] ledshowst;
output outtosec,outtomin,outtohou;

reg[7:0] datahigh,datalow;
reg[2:0] ledshowst;
reg  outtosec,outtomin,outtohou;
//wire   outtosec,outtomin,outtohou;
reg  secsel,minsel,housel;                   //newly add
reg[4:0] pstate,nstate;

parameter disminsec=5'b00001,
          dishoumin=5'b00010,
          manjudm=5'b00100,
          manjudh=5'b01000;
   //       autojud=5'b10000;
          
always @ (posedge clk or negedge reset)
  begin
  if(reset==0) begin pstate<=disminsec; /*secsel=1'b0; minsel=1'b0; housel=1'b0; */end   
  else pstate<=nstate;
  end
  
  


always @ (pstate or hmshift or msshift or dorjshift or jordshift)
  begin
  case(pstate)
  disminsec:
           begin
           if(~hmshift) nstate<=dishoumin;
           else if(~dorjshift) nstate<=manjudm;
           else nstate<=disminsec;
           end
  dishoumin:
           begin
           if(~msshift) nstate<=disminsec;
           else if(~dorjshift) nstate<=manjudm;
           else nstate<=dishoumin;					     
           end
  manjudm:
           begin
           if(~hmshift) nstate<=manjudh;
           else if(~jordshift) nstate<=disminsec;
           else nstate<=manjudm;
           end
  manjudh:
           begin
           if(~msshift) nstate<=manjudm;
           else if(~jordshift) nstate<=disminsec;
           else nstate<=manjudh;
           end
/* autojud:
           begin
           if(~hmshift) nstate<=manjudm;
           else if(~dorjshift) nstate<=disminsec;
           else nstate<=autojud;
           end			*/
  default:nstate<=disminsec;
  endcase
  end


always @ (pstate or mindata or secdata or houdata or freq1hz  or judgepulse)
   begin
   case(pstate)
   disminsec:
     begin
       ledshowst<=3'b010;
       datahigh<=mindata;
       datalow<=secdata;
       secsel<=1'b0;
       minsel<=1'b0;
       housel<=1'b0;
   //    outtosec=freq1hz;
   //    outtomin=infmsec;
   //     outtohou=infmmin;
     end
   dishoumin:
      begin
       ledshowst<=3'b001;
       datahigh<=houdata;
       datalow<=mindata;
       secsel<=1'b0;
       minsel<=1'b0;
       housel<=1'b0;
   //    outtosec=freq1hz;
   //    outtomin=infmsec;
   //    outtohou=infmmin;
      end
  manjudm:
     begin
       ledshowst<=3'b110;
       datahigh<=houdata;
       datalow<=mindata;
       secsel<=1'b1;
       minsel<=1'b1;
       housel<=1'b0;
   //    outtosec=1'b0;
   //    outtomin=judgepluse;
   //    outtohou=1'b0;
     end
   manjudh:
     begin
       ledshowst<=3'b101;
       datahigh<=houdata;
       datalow<=mindata;
       secsel<=1'b1;
       minsel<=1'b0;
       housel<=1'b1;
  //     outtosec=1'b0;
  //     outtomin=1'b0;
  //     outtohou=judgepluse;
     end	    
 /* autojud:
     begin
       ledshowst=3'b100;
       datahigh=houdata;
       datalow=mindata;
       outtosec=1'b0;
       outtomin=freq10hz;
       outtohou=infmmin;
     end		  */
   default:
     begin
       ledshowst<=3'b010;
       datahigh<=mindata;
       datalow<=secdata;
       secsel<=1'b0;
       minsel<=1'b0;
       housel<=1'b0;
    //   outtosec=freq1hz;
    //   outtomin=infmsec;
    //   outtohou=infmmin;
     end
   endcase
   end

always @ (freq1hz or secsel) 
  begin
  if(secsel) outtosec=1'b0;
  else       outtosec=freq1hz;
  end  
  
always @ (infmsec or judgepulse or minsel)
  begin                                                 //mux2
  if(minsel) outtomin=~judgepulse;
  else       outtomin=infmsec;
  end

always @ (infmmin or judgepulse or housel)
  begin
  if(housel) outtohou=~judgepulse;
  else       outtohou=infmmin;
  end


endmodule