qudou.v

使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.

module qudou(f1k,reset,pulsein,pulseout);

input   f1k,reset,pulsein;
output  pulseout;

reg pulseout;
reg[3:0] count; 

always @ (posedge f1k or negedge reset)
  begin
  if(~reset)
    begin
    count=4'h0;
    pulseout=1'b1;
    end
  else
    begin
    if(~pulsein)
      begin
      if(count==4'hf)
        begin
        pulseout=1'b0;
        count=4'h0;
        end
      else
        begin
        count=count+1;
        end
      end  
    else
      pulseout=1'b1; 
    end
  end
    
endmodule