Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select - 免费下载

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Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.

源码文件列表

📂 共 14 个源码文件 点击文件名可在线查看源代码

1 📄
data_memory.v
大小: 1.68 KB
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2 📄
alu_control.v
大小: 1.08 KB
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3 📄
line_control.v
大小: 583 B
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4 📄
instruction_memory.v
大小: 680 B
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5 📄
control.v
大小: 1.46 KB
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6 📄
sign_extend.v
大小: 495 B
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7 📄
testbranch.v
大小: 7.71 KB
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8 📄
alu.v
大小: 1.45 KB
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9 📄
test.v
大小: 5.98 KB
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10 📄
single_cycle_cpu.v
大小: 3.68 KB
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11 📄
test.prj
大小: 1.29 KB
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12 📄
pc.v
大小: 479 B
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13 📄
add.v
大小: 522 B
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14 📄
registers.v
大小: 1.46 KB
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