sign_extend.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//=============================================================================
//sign extend Module: from 16-bits extend to 32-bits
//	input [15:0] dataIn;
//	output [31:0] dataOut;
//=============================================================================

module Sign_extend( dataIn, dataOut );
	input [15:0] dataIn;
	output [31:0] dataOut;

	assign dataOut[15:0] = dataIn;
	assign dataOut[31:16] = ( dataIn[15] ) ? 16'b1111111111111111 : 16'b0000000000000000;

endmodule