alu_control.v

来自「Use the verilog language write a MIPS CP」· Verilog 代码 · 共 37 行

//=============================================================================
//ALU control Module
//	input [1:0] ALUOp,[5:0] funct;
//	output [2:0] oper,JR, shf;
//	
//=============================================================================

module Alu_control( funct, ALUOp, oper, JR, shf );
	input [1:0] ALUOp;
	input [5:0] funct;
	output [2:0] oper;	//operator
	output JR, shf;	//jump register? shift?
	reg [2:0] oper;

	always @( ALUOp or funct )	
		begin
			casex( { ALUOp, funct } )
				8'b00xxxxxx:	oper = 010;	//add
				8'b01xxxxxx:	oper = 110;	//sub
				8'b1x0x0000:	oper = 100;	//shift left
				8'b1x1x0000:	oper = 010;	//add
				8'b1x0x0010:	oper = 101;	//shift right
				8'b1x1x0010:	oper = 110;	//sub
				8'b1xxx0100:	oper = 000;	//and
				8'b1xxx0101:	oper = 001;	//or
				8'b1xxx1000:	oper = 010;	//add
				8'b1xxx1010:	oper = 111;	//slt
				default:	oper = 011;	//Assign 0
			endcase
		end
	
	assign JR = ( {ALUOp,funct} == 8'b10001000 ) ? 1 : 0;
	assign shf = ( {ALUOp,funct} == 8'b10000000 | {ALUOp,funct} == 8'b10000010 ) ? 1 : 0;

endmodule