data_memory.v

来自「Use the verilog language write a MIPS CP」· Verilog 代码 · 共 46 行

//=============================================================================
//Data memory Module: Memory size is 64 words of 8 bits ( 1 bite ) each
//		      Swap line is control swap or not swap
//	input CLK, MemRead, MemWrite, swap;
//	input [31:0] Address1, Address2, Write_data;
//	output [31:0] Read_data1, Read_data2;
//=============================================================================

module Data_memory( CLK, MemRead, MemWrite, swap, Address1, Address2, Write_data, Read_data1, Read_data2 );
	input CLK, MemRead, MemWrite, swap;	//clock, enable read, enable write, enable write data2
	input [31:0] Address1, Address2, Write_data;	//target address, write data
	output [31:0] Read_data1, Read_data2;	//read data
	reg [31:0] Read_data1, Read_data2;
	reg [7:0] Mem [0:80];	//64 * 8 memory

	always @( Address1 or Address2 or MemRead )	
		begin
			if( MemRead )
				begin
					Read_data1 = { Mem[Address1+3], Mem[Address1+2], Mem[Address1+1], Mem[Address1] };	//read data1
					Read_data2 = { Mem[Address2+3], Mem[Address2+2], Mem[Address2+1], Mem[Address2] };	//read data2
				end
			else
				begin
					Read_data1 = 4'bz;	//High impedance state
					Read_data2 = 4'bz;	//High impedance state
				end
		end	//read data


	always @( posedge CLK )	
		begin
			if( MemWrite )	
				begin
					{ Mem[Address1+3], Mem[Address1+2], Mem[Address1+1], Mem[Address1] } = Write_data;
				end
			if( swap )	
				begin			
					{ Mem[Address2+3], Mem[Address2+2], Mem[Address2+1], Mem[Address2] } = Read_data1;			
					{ Mem[Address1+3], Mem[Address1+2], Mem[Address1+1], Mem[Address1] } = Read_data2;
				end	//swap two data into Mem
		end	//write data

endmodule