line_control.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//=============================================================================
//Line control Module: control to be or not to be change two line
//	input control;
//	input [31:0] Datain1, Datain2;
//	output [31:0] Dataout1, Dataout2;
//=============================================================================

module Line_control( control, Datain1, Datain2, Dataout1, Dataout2);
	input control;
	input [31:0] Datain1, Datain2;
	output [31:0] Dataout1, Dataout2;

	assign Dataout1 = ( control ) ? Datain2 : Datain1;
	assign Dataout2 = ( control ) ? Datain1 : Datain2;

endmodule