single_cycle_cpu.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//===================================================================
//signal cycle cpu:
//	Design single cycle cpu
//
//	Instruction 	op_code		funct		Gategory		Example		Meaning
//	add		R 000000	100000		Arithmetic		$s1,$s2,$s3	$s1=$s2+$s3
//	sub		R 000000	100010		Arithmetic		$s1,$s2,$s3	$s1=$s2-$s3
//	lw		I 100011			Data transfer		$s1,100($s2)	$s1=Memory[$s2+100]
//	sw		I 101011			Data transfer		$s1,100($s2)	Memory[$s2+100]=$s1
//	beq		I 000100			Conditional branch	$s1,$s2,25	if($s1=$s2)go to PC+4+(4*25)
//	bne		I 000101			Conditional branch	$s1,$s2,25	if($s1!=$s2)go to PC+4+(4*25)
//	slt		R 000000	101010		Conditional branch	$s1,$s2,$s3	if($s2<$s3) $s1=1 else $s1=0
//	j		J 000010			Unconditional jump	j 2500		go to (4*2500)
//	jr		R 000000	001000		Unconditional jump	jr $ra		go to $ra
//	jal		J 000011			Unconditional jump	jal 2500	$ra=PC+4;go to (4*2500)
//	addi		I 001000			Arithmetic		$s1,$s2,100	$s1=$s2+100
//	sll		R 000000	000000		Logic			$s1,$s2,10	$s1=$s2<<10
//	srl		R 000000	000010		Logic			$s1,$s2,10	$s1=$s2>>10
//	sort		R 100111	101010		Compare&Swap		$s1,$s2,$s3	if(cmp=1) swap($s2,$s3)	
//
//	input: CLK
//	output: NULL
//
//===================================================================

`include "Pc.v"
`include "Add.v"
`include "Instruction_memory.v"
`include "Control.v"
`include "Registers.v"
`include "Alu.v"
`include "Alu_control.v"
`include "Sign_extend.v"
`include "Data_memory.v"
`include "Line_control.v"

module Single_cycle_cpu( CLK );
	input CLK;
	
	wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jal, Bne, Zero, PCSrc, JR, cmp, swap, shf;
	wire [1:0] ALUOp;
	wire [2:0] oper;
	wire [4:0] Instruction_5bitsMUX_WriteRegister;
	wire [31:0] Instruction;
	wire [31:0] PC_Read_address, PC_add4, PC_BeqResult, PC_NewAddress;
	wire [31:0] Address1, Address2, Reg_DM1, data1, data2, ExtendOrRead_data2, Readdata1orShmat;
	wire [31:0] Read_data1, Read_data2, ALU_Data_Address_32bitsMUX_WriteData, ALU_result, DATA_extend, ALU_SrcA, ALU_SrcB, extend_shift2, JumpAddress;
	
	
	assign 	PCSrc = Branch & ( Zero ^ Bne );
	assign 	PC_NewAddress = (Jump) ? JumpAddress : (JR) ? ALU_result : (PCSrc) ? PC_BeqResult : PC_add4;
	assign 	JumpAddress = { PC_add4[31:28], Instruction[25:0], 2'b00 };
	assign 	Instruction_5bitsMUX_WriteRegister = ( Jal ) ? 5'b11111 : ( RegDst ) ? Instruction[15:11] : Instruction[20:16];
	assign 	ALU_Data_Address_32bitsMUX_WriteData = ( Jal ) ? PC_add4 : ( MemtoReg ) ? data1 : ALU_result;
	assign  extend_shift2 = DATA_extend << 2;
	assign 	ExtendOrRead_data2 = ( ALUSrc ) ? DATA_extend : Read_data2;
	assign 	Address1 = ( cmp ) ? Reg_DM1 : ALU_result;
	assign 	swap = ALU_result[0] & cmp;
	assign 	Readdata1orShmat = ( shf ) ? {27'b000000000000000000000000000,Instruction[10:6]} : Read_data1;
	
	Pc	PCounter( CLK, PC_NewAddress, PC_Read_address );
	Add	add4( PC_Read_address, 32'h00000004, PC_add4 );
	Add 	addBeq( PC_add4, extend_shift2, PC_BeqResult );
	Instruction_memory InstMem( PC_Read_address, Instruction );
	Sign_extend SignExtend( Instruction[15:0], DATA_extend );
	Registers Register( Instruction[25:21] , Instruction[20:16], Instruction_5bitsMUX_WriteRegister, ALU_Data_Address_32bitsMUX_WriteData, RegWrite, CLK, Read_data1, Read_data2  );
	Alu ALUwithCLA( ALU_SrcA, ALU_SrcB, oper, ALU_result, Zero );
	Data_memory DataMem( CLK, MemRead, MemWrite, swap, Address1, Address2, Read_data2, data1, data2 );
	Line_control ALUsrc1( cmp, Readdata1orShmat, data1, ALU_SrcA, Reg_DM1 );
	Line_control ALUsrc2( cmp, ExtendOrRead_data2, data2, ALU_SrcB, Address2 );
	Control CUPControl(Instruction[31:26], RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Jal, Bne, cmp );
	Alu_control ALUControl( Instruction[5:0], ALUOp, oper, JR, shf );
	

endmodule