alu.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//=============================================================================
//32-bits ALU Module
//                                                                        
//	32-bits ALU ( with carry lookahead):
//	(1) Two's complement computation required.
//	(2) I/O of the 32-bit ALU:
//			input: 32-bits A, 32-bits B, 3-bits ALUOp
//			output: 32-bits Result, 1-bit Zero, 1-bit Overflow, 1-bit CarryOut
//	(3) Result:
//			depend on ALUOp
//			0 00:	Result = A and B;
//			0 01:	Result = A or B;
//			0 10:	Result = A + B;
//			0 11:	Result = 32'h00000000;
//			1 00:	Result   shift left
//			1 01:	Result   shift right
//			1 10:	Result = A - B;
//			1 11:	Result = ( A < B ) ? 1 : 0;
//		Zero = ( A == B ) ? 1 : 0;
//
//=============================================================================

module Alu( A, B, ALUOp, Result, Zero );
	input [31:0] A, B;
	input [2:0] ALUOp;	//one 3-bits operate
	output [31:0] Result;
	output Zero;	//function output
	reg [31:0] Result;

	assign Zero = ( Result == 32'h00000000 ) ? 1'b1 : 1'b0;
	always@( A or B or ALUOp )
		casex( ALUOp )
			3'b000:	Result = A & B;		//AND
			3'b001: Result = A | B;		//OR
			3'b010: Result = A + B;		//ADD
			3'b011:	Result = 32'h00000000;	//Assign 0
			3'b100:	Result = B << A;	//SHIFT	LEFT
			3'b101:	Result = B >> A;	//SHIFT	RIGHT
			3'b110: Result = A - B;		//SUB
			3'b111: Result = ( A < B ) ? 32'h00000001 : 32'h00000000;	//SLT
		endcase

endmodule