control.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//=============================================================================
//Control Module
//	input [5:0] Instruction;
//	output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jal, Bne, Cmp;
//	output [1:0]ALUOp;
//=============================================================================

module Control( Instruction, RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Jal, Bne, Cmp );
	input [5:0] Instruction;
	output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jal, Bne, Cmp;
	output [1:0]ALUOp;

	assign RegDst = ( ( Instruction == 6'b000000 ) | ( Instruction == 6'b100111 ) );
	assign Jump = ( Instruction[5:1] == 5'b00001 );
	assign Branch = ( Instruction[5:1] == 5'b00010 );
	assign MemRead = ( ( Instruction == 6'b100011 ) | ( Instruction == 6'b100111 ) );
	assign MemtoReg = ( Instruction == 6'b100011 );
	assign ALUOp[1] = ( ( Instruction == 6'b000000 ) | ( Instruction == 6'b100111 ) );
	assign ALUOp[0] = ( Instruction[5:1] == 5'b00010 );
	assign MemWrite = ( Instruction == 6'b101011 );
	assign ALUSrc = ( ( Instruction == 6'b100011 ) | ( Instruction == 6'b101011 ) | (Instruction == 6'b001000 ) );
	assign RegWrite = ( ( Instruction == 6'b000000 ) | ( Instruction == 6'b001000 ) | ( Instruction == 6'b100111 ) | ( Instruction[4:0] == 5'b00011 ) );
	assign Jal = ( Instruction == 6'b000011 );
	assign Bne = ( Instruction == 6'b000101 );
	assign Cmp = ( Instruction == 6'b100111 );

endmodule	// Control