top_watch.tan.rpt

来自「60秒秒表设计」· RPT 代码 · 共 300 行 · 第 1/5 页

; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|carry                           ; dtlatch:dtlatch1|sel_din[6]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[0]                        ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[1]                        ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[2]                        ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[3]                        ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[0]                       ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[1]                       ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[2]                       ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[3]                       ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[0]                         ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[1]                         ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[2]                         ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[3]                         ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[0] ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[1] ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[2] ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[3] ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|carry                           ; dtlatch:dtlatch1|sel_din[7]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[0]                        ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[1]                        ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[2]                        ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[3]                        ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[0]                       ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[1]                       ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[2]                       ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[3]                       ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[0]                         ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[1]                         ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[2]                         ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[3]                         ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[0] ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[1] ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[2] ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[3] ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|carry                           ; dtlatch:dtlatch1|sel_din[8]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[0]                        ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[1]                        ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[2]                        ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[3]                        ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[0]                       ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[1]                       ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[2]                       ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[3]                       ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[0]                         ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[1]                         ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[2]                         ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|low2[3]                         ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[0] ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[1] ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[2] ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[3] ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count60:count_2|carry                           ; dtlatch:dtlatch1|sel_din[9]  ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[0]                        ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[1]                        ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[2]                        ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|low1[3]                        ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[0]                       ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[1]                       ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[2]                       ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; counter:counts|count100:count_1|high1[3]                       ; dtlatch:dtlatch1|sel_din[10] ; clk        ; clk      ; None                        ; None                      ; 17.000 ns               ;