switch.v

来自「60秒秒表设计」· Verilog 代码 · 共 18 行

module switch(clk4,rst,swin,pulse);
input clk4,rst,swin;
output pulse;

reg swout;

assign pulse=swout;

always@(posedge clk4 or negedge rst)
  begin
    if(rst==1'b0)
       swout<=1'b0;
    else
       swout<=swin;
  end

endmodule