dtlatch.v

来自「60秒秒表设计」· Verilog 代码 · 共 15 行

module dtlatch(clk4,en,rst,din,sel_din);
input clk4,en,rst;
input [15:0]din;
output [15:0]sel_din;
reg [15:0]sel_din;


always@(posedge clk4 or negedge rst)
  begin
    if(!rst)
      sel_din<=16'h0;
    else if(en)
      sel_din<=din;
  end
endmodule