counter.v

来自「60秒秒表设计」· Verilog 代码 · 共 27 行

//The top module 60s counter
module counter(clk,rst,en,load,q);
input clk,rst,en,load;
output[15:0] q;

reg[15:0] q;

wire[15:0] qout;
wire[1:0] cnt,carry;

count100 count_1(.clk(clk),.rst(rst),.en(en),.load(load),.q(qout[7:0]),.carry(cnt[0]));
count60  count_2(.clk(clk),.rst(rst),.en(cnt[0]),.load(load),.q(qout[15:8]),.carry(cnt[1]));

assign carry[1]=(q==16'h6000)?1'b1:cnt[1];

always@(carry[1])
  begin
    if(carry[1]==1)
      begin
        q[15:8]<=8'h60;
        q[7:0]<=8'h00;
      end
    else
      q<=qout;
  end

endmodule